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Espressif Systems /ESP32-S2 /SPI0 /SLV_WRBUF_DLEN

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Interpret as SLV_WRBUF_DLEN

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SLV_WR_BUF_DONE)SLV_WR_BUF_DONE 0CONF_BASE_BITLEN

Description

SPI slave Wr_BUF interrupt and CONF control register

Fields

SLV_WR_BUF_DONE

The interrupt raw bit for the completion of write-buffer operation in the slave mode. Can not be changed by CONF_buf.
CONF_BASE_BITLEN

The basic spi_clk cycles of CONF state. The real cycle length of CONF state, if SPI_USR_CONF is enabled, is SPI_CONF_BASE_BITLEN[6:0] + SPI_CONF_BITLEN[23:0].

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data